1. Field
Various exemplary embodiments of the present invention relate to a latch circuit and a semiconductor device including the same.
2. Description of the Related Art
With the increase in integration degree of semiconductor devices and the decrease in size of transistors, the quantity of electric charge that can be stored in the transistor has gradually decreased. Thus, data stored in a latch or the like of the semiconductor device may be influenced by alpha particle collisions or cosmic rays. For example, when alpha particles collide with the semiconductor device, a cloud of hole-electron pairs are generated around paths of the alpha particles passing through the semiconductor material. The generated holes and electrons are transferred to electric fields existing in the semiconductor device. The polarity of a node of the latch, in which an electric charge is stored, may be changed by the transfer of the holes and electrons, and the data stored in the latch may be inverted. This phenomenon in which data stored in the latch is changed by alpha particle collisions or cosmic rays is referred to as a soft error, and the frequency of soft errors has increased to such a level that it is affecting the reliability of the entire semiconductor device.
A conventional memory device stores an address corresponding to a defective part of a cell array in a fuse circuit, and compares the address stored in the fuse circuit to an address which is inputted to the memory device that designates a position to be accessed in the memory device, in order to control a repair operation of the memory device. The repair operation replaces part of the cell array where a defect has occurred with a normally functioning part of the cell array. Conventionally, a laser fuse has been used to store defective addresses. Laser fuses store high or low data according to whether a fuse is cut. The laser fuse can be programmed at a wafer level, but cannot be programmed after the wafer is mounted in a package. Furthermore, due to pitch, laser fuses have limits in how small they are capable of being designed.
In order to solve this problem, a nonvolatile memory circuit such as an E-fuse array circuit (ARE), NAND flash memory, NOR flash memory, EPROM (Erasable Programmable Read Only Memory), EEPROM (Electrically Erasable Programmable Read Only Memory), FRAM (Ferroelectric RAM), and MRAM (Magneto-resistive RAM) may be included in the memory device, and repair information may be stored in the nonvolatile memory circuit.
FIG. 1 is a block diagram illustrating a memory device using a non-volatile memory circuit to store repair information according to prior art.
Referring to FIG. 1, the memory device includes a plurality of memory banks BK0 to BK3, a plurality of latch sets 110_0 to 110_3 provided for the respective memory banks BK0 to BK3 to store repair information, a latch set 110_4 for storing setting information, a setting circuit 120, and a nonvolatile memory circuit 101.
The nonvolatile memory circuit 101 replaces a conventional fuse circuit, and stores repair information, i.e., repair addresses, corresponding to all of the banks BK0 to BK3. Furthermore, the nonvolatile memory circuit 101 stores setting information required for operation of the memory device. The nonvolatile memory circuit may be one among an e-fuse array circuit, a NAND flash memory, a NOR flash memory, an Erasable Programmable Read Only Memory (EPROM), an Electrically Erasable Programmable Read Only Memory (EEPROM), a Ferroelectric Random Access Memory (FRAM) and a Magnetoresistive Random Access Memory (MRAM).
The latch sets 110_0 to 110_3 provided for the respective banks BK0 to BK3 store repair information of the memory banks corresponding thereto. The latch set 110_0 stores the repair information of the memory bank BK0, and the latch set 110_2 stores the repair information of the memory bank BK2. Furthermore, the latch set 110_3 stores setting information to be used for the setting circuit 120. The setting circuit 120 may set various setting values required for an operation of the memory device, for example, an internal voltage level and various latencies, using the setting information stored in the latch set 110_3. The latch sets 110_0 to 110_4 may store the repair information only while power is supplied. The repair information to be stored in the latch sets 110_0 to 110_4 may be received from the nonvolatile memory circuit 101. The nonvolatile memory circuit 101 transmits the stored repair information to the latch sets 110_0 to 110_3 when a boot-up signal BOOTUP is enabled.
Since the nonvolatile memory circuit 101 is configured in an array, a certain amount of time is required to load data stored in the nonvolatile memory circuit 101, and thus data cannot be immediately loaded, and the data stored in the nonvolatile memory circuit 101 cannot be directly used to perform a repair operation. Thus, the repair information and the setting information stored in the nonvolatile memory circuit 101 is transmitted and stored into the latch sets 110_0 to 110_4, and the data stored in the latch sets 110_0 to 110_4 is used for the repair operations of the memory banks BK0 to BK3 and the setting operation of the setting circuit 120. The operation of transmitting the repair information and the setting information from the nonvolatile memory circuit 101 to the latch sets 110_0 to 110_4 is referred to as a boot-up operation. Only when a boot-up operation is completed may the memory device repair a failed cell and perform various setting operations. Then, the memory device may start a normal operation.
Memory devices may have a large number of latches for executing repair operations. Since there are many latches, soft errors may have a large influence on the reliability of repair operations within a memory device. In addition, since latches are used as memory cells in a semiconductor device such as SRAM, the reliability of these devices may also be affected by soft errors.